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cy7c10212cv33 1-mbit (64 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-82303 rev. *a revised october 30, 2013 1-mbit (64 k 16) static ram features temperature ranges ? automotive-e: ?40 c to 125 c pin and function compatible with cy7c10212cv33 high speed ? t aa = 12 ns (automotive-e) cmos for optimum speed and power low active power: 325 mw (max) automatic power down when deselected independent control of upper and lower bits available in pb-free 48-ball fbga package functional description the cy7c10212cv33 is a high performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . for more info rmation, see the truth table on page 9 for a complete description of read and write modes. the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). logic block diagram 64k x 16 ram array i/o 0 ?i/o 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 i/o 8 ?i/o 15 ce we ble bhe a 8
cy7c10212cv33 document number: 001-82303 rev. *a page 2 of 14 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 truth table ........................................................................ 9 ordering information ...................................................... 10 ordering code definitions ......................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc? solutions ...................................................... 14 cypress developer community ................................. 14 technical support ................. .................................... 14
cy7c10212cv33 document number: 001-82303 rev. *a page 3 of 14 selection guide description - 12 unit maximum access time 12 ns maximum operating current 90 ma maximum cmos standby current 10 ma pin configuration figure 1. 48-ball fbga pinout [1] we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc nc a 2 a 1 ble i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h nc nc v cc v cc v ss note 1. nc pins are not connected on the die.
cy7c10212cv33 document number: 001-82303 rev. *a page 4 of 14 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ...............................?0.3 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.3 v to v cc + 0.3 v dc input voltage [2] ............................ ?0.3 v to v cc + 0.3 v current into outputs (low) .... .................................... 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch up current ................................................... > 200 ma operating range range ambient temperature (t a ) v cc automotive-e ?40 ? c to +125 ? c 3.3 v ? 10% electrical characteristics over the operating range parameter description test conditions -12 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?12 +12 ? a i/o z output leakage current gnd < v i < v cc , output disabled ?12 +12 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc ?90ma i sb1 automatic ce power down current ? ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max ?20ma i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?10ma note 2. v il(min) = ?2.0 v and v ih(max) = v cc + 0.5 v for pulse durations of less than 20 ns.
cy7c10212cv33 document number: 001-82303 rev. *a page 5 of 14 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out output capacitance 8pf thermal resistance parameter [3] description test conditions 48-ball fbga unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 95.32 ? c/w ? jc thermal resistance (junction to case) 10.68 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms [4] notes 3. tested initially and after any design or proces s changes that may affect these parameters. 4. speed is tested using the thevenin load shown in figure 2 (a). high z characteristics are tested using the test load shown in figure 2 (b).
cy7c10212cv33 document number: 001-82303 rev. *a page 6 of 14 switching characteristics over the operating range parameter [5] description -12 unit min max read cycle t power [6] v cc (typical) to the first access 100 ? ? s t rc read cycle time 12 ? ns t aa address to data valid ? 12 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 12 ns t doe oe low to data valid ? 6 ns t lzoe oe low to low z [7] 0 ? ns t hzoe oe high to high z [7, 8] ? 6 ns t lzce ce low to low z [7] 3 ? ns t hzce ce high to high z [7, 8] ? 6 ns t pu [9] ce low to power up 0 ? ns t pd [9] ce high to power down ? 12 ns t dbe byte enable to data valid ? 6 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 6 ns write cycle [10] t wc write cycle time 12 ? ns t sce ce low to write end 9 ? ns t aw address setup to write end 9 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 8 ? ns t sd data setup to write end 6 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [7] 3 ? ns t hzwe we low to high z [7, 8] ? 6 ns t bw byte enable to end of write 8 ? ns notes 5. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. 6. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 7. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of figure 2 on page 5 . transition is measured ? 500 mv from steady state voltage. 9. this parameter is guaranteed by design and is not tested. 10. the internal write time of the memory is defined by the overlap of ce low, we low, and bhe /ble low. ce , we , and bhe /ble is low to initiate a write. the transition of these signals terminate the write. the input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
cy7c10212cv33 document number: 001-82303 rev. *a page 7 of 14 switching waveforms figure 3. read cycle no. 1 (address transition controlled) [11, 12] figure 4. read cycle no. 2 (oe controlled) [12, 13] previ/ous da ta valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe ,ble current notes 11. device is continuously selected. oe , ce , bhe , and/or ble = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low.
cy7c10212cv33 document number: 001-82303 rev. *a page 8 of 14 figure 5. write cycle no. 1 (ce controlled) [14, 15] figure 6. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we notes 14. data i/o is high impedance if oe, bhe, and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high impedance state.
cy7c10212cv33 document number: 001-82303 rev. *a page 9 of 14 figure 7. write cycle no. 3 (we controlled, low) truth table ce oe we ble bhe i/o 0 ? i/o 7 i/o 8 ? i/o 15 mode power h x x x x high z high z power down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble
cy7c10212cv33 document number: 001-82303 rev. *a page 10 of 14 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 12 CY7C10212CV33-12BAXE 51-85106 48- ball fbga (pb-fr ee) automotive-e temperature range: e = automotive-e pb-free package type: ba = 48-ball fbga speed: 12 ns voltage range: v33 = 3 v to 3.6 v process technology: c = 0.16 m technology fixed value data width: 1 = 16-bits density: 02 = 1-mbit family code: 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 12 ba 7 02 v33 e c 1 x 2
cy7c10212cv33 document number: 001-82303 rev. *a page 11 of 14 package diagrams figure 8. 48-ball fbga (7 8.5 1.2 mm) ba48a package outline, 51-85106 51-85106 *g
cy7c10212cv33 document number: 001-82303 rev. *a page 12 of 14 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius a microampere s microsecond ma milliampere mm millimeter mw milliwatt mhz megahertz ns nanosecond % percent pf picofarad vvolt wwatt
cy7c10212cv33 document number: 001-82303 rev. *a page 13 of 14 document history page document title: cy7c10212cv33, 1-mbit (64 k 16) static ram document number: 001-82303 rev. ecn no. submission date orig. of change description of change ** 3723052 10/29/2012 tava new data sheet. *a 4178071 10/30/2013 vini updated in new template. completing sunset review.
document number: 001-82303 rev. *a revised october 30, 2013 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c10212cv33 ? cypress semiconductor corporation, 2012-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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